Goovtant: an efficient mixed level ATPG to test realistic faults in complex CMOS circuits

An efficient solution for test pattern generation based on a switch-level description of complex CMOS circuits is presented. To obtain gate-level speeds and to test realistic CMOS failures, this mixed-level approach recommends structural and functional grading during the preprocessing phase. Conducting path analysis, relaxation algorithms, and truth-table analysis all contribute to functional grading. Results show that the time required for these additional preprocessing steps is close to negligible compared to total CPU time. During test pattern generation (TPG), fault injection can be performed at switch level with precise knowledge of CMOS technology, while the propagation and backtrace steps are applied to the circuit functional model. Thus, classical TAG algorithms can be used. Two learning techniques that mainly deal with the fault injection step and are compatible with most of the other published techniques are introduced. Their use is optional in this mixed-level approach, but they can significantly speed up TPG