High-Speed Data Transmission System Design and Implementation Based on FPGA

Author

Yan, Bei ; Sun, Yuefeng

Author_Institution

Sch. of Autom. Sci. & Electr. Eng., Beihang Univ., Beijing, China

fYear

2009

fDate

19-20 Dec. 2009

Firstpage

1

Lastpage

4

Abstract

Aimed at the non-standard Flash memory composed of 8 K9KAG08U0M Flash chips of Samsung Company, the paper introduces a high-speed data transfer interface with FPGA (Field Programmable Gate Array) as the main controller. With the synchronous DMA (Direct Memory Access) mode of USB2.0, the system implements the management, reading and transmission of the data in the memory. The design of the system proves in practice that the effective transmission speed reaches 30 MB/s and in just 15 minutes, all of the data in the 16.5 G bytes non-standard memory can be downloaded to the hard disk of the computer.

Keywords

data communication; field programmable gate arrays; file organisation; flash memories; FPGA; bit rate 30 Mbit/s; direct memory access; high-speed data transfer interface; high-speed data transmission system design; non-standard Flash memory; non-standard memory; synchronous DMA; time 15 min; Automatic control; Centralized control; Circuits; Control systems; Data communication; Design automation; Electronic mail; Field programmable gate arrays; Flash memory; Protocols;

fLanguage

English

Publisher

ieee

Conference_Titel

Information Engineering and Computer Science, 2009. ICIECS 2009. International Conference on

Conference_Location

Wuhan

Print_ISBN

978-1-4244-4994-1

Type

conf

DOI

10.1109/ICIECS.2009.5365545

Filename

5365545