Efficient simulation of parametric faults for multi-stage analog circuits

Due to process variability which makes the analog circuit response probabilistic, fault simulation effectively requires a statistical analysis for each fault. As a result, fault simulation presents the major computational time component in analog test automation. While recently a number of statistical analysis approaches for analog circuits have been proposed, overall computational time is a big concern when a high number of parametric faults need to be evaluated. We present a series of schemes to increase the efficiency of fault simulation by extracting and reusing information from one fault simulation to another. Experiments on a baseband amplifier circuit confirm that the proposed techniques can be collectively applied to provide about a 50-fold simulation time saving at the cost of less than 3% loss in accuracy when compared with similar prior techniques.