DocumentCode
2853696
Title
Dependable clock distribution for crosstalk aware design
Author
Miura, Yukiya
Author_Institution
Fac. of Syst. Design, Tokyo Metropolitan Univ., Tokyo
fYear
2007
fDate
21-26 Oct. 2007
Firstpage
1
Lastpage
9
Abstract
In order to guarantee proper junction of a system, a correct clock signal must be distributed. This paper proposes two methods for distributing the clock signal that take account of crosstalk noises generated on the clock signal line, which are applicable to conventional synchronous digital systems. For the clock signal of a pulse type, we propose a multiple clock pulse method that has the tolerance for an incorrect clock pulse induced by a crosstalk fault. For the clock signal of a level sensitive type, we propose a self-correction method for the change of the clock signal width during system operation. The circuits implemented by both methods can be inserted into clock signal lines as adapter circuits for the conventional clocked element and flip-flop, and as a result, the proposed methods are easily built in conventional synchronous digital circuits. We show effectiveness of our design by circuit simulation for the conventional flip-flop.
Keywords
circuit simulation; clocks; crosstalk; flip-flops; adapter circuits; circuit simulation; clock signal; crosstalk aware design; crosstalk noises; dependable clock distribution; flip-flop; multiple clock pulse method; self-correction method; synchronous digital systems; Circuit faults; Circuit testing; Clocks; Crosstalk; Digital circuits; Electrical fault detection; Fault detection; Fault tolerance; Signal generators; Synchronous generators;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 2007. ITC 2007. IEEE International
Conference_Location
Santa Clara, CA
ISSN
1089-3539
Print_ISBN
978-1-4244-1127-6
Electronic_ISBN
1089-3539
Type
conf
DOI
10.1109/TEST.2007.4437644
Filename
4437644
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