IJTAG: The path to organized instrument connectivity

Author

Crouch, Alfred L.

Author_Institution

Inovys Corp., Austin, TX

fYear

2007

fDate

21-26 Oct. 2007

Firstpage

1

Lastpage

10

Abstract

In recent times, the 1149.1 TAP and TAP controller have begun to play a more important role in accessing embedded logic that is not specifically limited to 1149.1´s scope as a board-test standard. This logic, referred to by the generic term instruments, includes manufacturing test and design-for-test (DFT) logic; design-for-debug/diagnosis (DFD) logic; design-for-yield (DFY) logic and monitors; and in-system verification logic (such as hardware assertions). The P1687 IJTAG standard working group was created to investigate formalizing and standardizing this use of the 1149.1 controller - and after a little more than a years worth of effort has produced a hardware architecture proposal that is currently being used as a strawman to investigate and develop the description and protocol language effort.

Keywords

design for testability; logic design; logic devices; logic testing; 1149.1 TAP controller; IJTAG; P1687 IJTAG standard working group; TAP controller; board-test standard; description language; design-for-debug logic; design-for-diagnosis logic; design-for-test logic; design-for-yield logic; embedded logic devices; generic term instruments; hardware architecture proposal; in-system verification logic; manufacturing test; organized instrument connectivity; protocol language; Design for disassembly; Design for testability; Hardware; Instruments; Logic design; Logic testing; Manufacturing; Proposals; Protocols; Standards Working Groups;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 2007. ITC 2007. IEEE International

Conference_Location

Santa Clara, CA

ISSN

1089-3539

Print_ISBN

978-1-4244-1127-6

Electronic_ISBN

1089-3539

Type

conf

DOI

10.1109/TEST.2007.4437656

Filename

4437656