High level DSP synthesis using the MARS design system

Methodologies for high-level synthesis of dedicated digital signal processing (DSP) architectures using the MARS (Minnesota architecture synthesis) design system are considered. Concurrent scheduling and resource allocation algorithms that exploit interaction and intraiteration precedence constraints are introduced. These algorithms produce solutions that are as good as or better than those previously published. MARS can generate valid architectures for algorithms that have distributed arc delays and exploits these delays to produce more efficient architectures. This allows the system to be more general and provides for the synthesis of more complicated algorithms Implicit retiming and pipelining of the data flow graph are used to improve the quality of the design. Architectures that meet the iteration bound of any algorithm can be synthesized by unfolding the original data flow graph