DocumentCode
2853967
Title
Design-for-reliability: A soft error case study
Author
Zhang, Ming
Author_Institution
Intel Corp., Folsom, CA
fYear
2007
fDate
21-26 Oct. 2007
Firstpage
1
Lastpage
1
Abstract
The purpose of this lecture is to illustrate a design-for-reliability (DFR) strategy via a soft error case study. We review relevant methodologies that target different levels and stages of a multi-core design: soft error modeling, robust circuit design, microarchitecture, and chip architecture. Finally we discuss several emerging DFR challenges and possible mitigation solutions.
Keywords
VLSI; integrated circuit design; integrated circuit reliability; radiation hardening (electronics); VLSI; chip architecture; design-for-reliability; microarchitecture; multi-core design; robust circuit design; soft error case study; soft error modeling; Circuit synthesis; Circuit testing; Error analysis; Error correction codes; Flip-flops; Logic circuits; Microarchitecture; Protection; Robustness; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 2007. ITC 2007. IEEE International
Conference_Location
Santa Clara, CA
ISSN
1089-3539
Print_ISBN
978-1-4244-1127-6
Electronic_ISBN
1089-3539
Type
conf
DOI
10.1109/TEST.2007.4437664
Filename
4437664
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