DocumentCode
2853985
Title
Two-dimensional compaction for placement refinement
Author
Xiong, X.-M.
Author_Institution
Appl. Micro Circuits Corp., San Diego, CA, USA
fYear
1989
fDate
5-9 Nov. 1989
Firstpage
136
Lastpage
139
Abstract
A two-dimensional compaction algorithm is presented which is developed primarily for placement refinement of a building-block layout. For a given placement, a mixed-adjacency graph is derived and then a set of graph operations are applied to the graph to accomplish two-dimensional compaction. The placement can be updated efficiently in the geometric domain because of the one-to-one correspondence between the mixed-adjacency graph and the title representation of the placement. Some pertinent properties of the mixed-adjacency graph and one-dimensional compaction using the graph model are also explored.<>
Keywords
circuit layout CAD; graph theory; network topology; building-block layout; geometric domain; graph model; mixed-adjacency graph; one-dimensional compaction; placement refinement; title representation; two-dimensional compaction algorithm; Algorithm design and analysis; Circuits; Compaction; Geometry; Iterative algorithms; Iterative methods; Linear programming; NP-hard problem; Routing; Tiles;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer-Aided Design, 1989. ICCAD-89. Digest of Technical Papers., 1989 IEEE International Conference on
Conference_Location
Santa Clara, CA, USA
Print_ISBN
0-8186-1986-4
Type
conf
DOI
10.1109/ICCAD.1989.76921
Filename
76921
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