At-speed scan tests: A reality at LSI

Author

Krishnamurthy, P.

Author_Institution

LSI Corp., Milpitas, CA

fYear

2007

fDate

21-26 Oct. 2007

Firstpage

1

Lastpage

1

Abstract

For 65 nm technologies and beyond, at-speed testing with high test coverage is a requirement for meeting low DPPM. Functional testing is not an option when it comes to merchant ASIC market. Functional vectors are time consuming to develop, need customer inputs, lack adequate coverage and time consuming to debug and deploy. Structural testing is our only option. Delay fault testing became a necessity for LSI, starting at the 0.18 mu node. Broadside transition delay fault testing run at tester clock rates was introduced for all products. Even though the observed overkill of TDF fails was close to 50% (validated with system level tests), the impact on reducing outgoing product quality was significant whilst at the same time the resultant yield impact was < 0.5%.

Keywords

application specific integrated circuits; automatic test pattern generation; integrated circuit testing; integrated circuit yield; large scale integration; at-speed scan tests; broadside transition delay fault testing; functional testing; large scale integration; resultant yield impact; size 0.18 mum; size 65 nm; structural testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 2007. ITC 2007. IEEE International

Conference_Location

Santa Clara, CA

ISSN

1089-3539

Print_ISBN

978-1-4244-1127-6

Type

conf

DOI

10.1109/TEST.2007.4437670

Filename

4437670