Development of scalable electrical models for high-voltage LDMOS

This paper presents a scalable electrical model for high-voltage laterally-diffused metal oxide semiconductor field effect transistor (HV-LDMOS) to determine the I–V characteristics, which can be used in SPICE simulators. This scalable model is represented as a hybrid model by computing its transfer function to enable its wide use in testing high-voltage devices. The scalable model has been validated for different device geometries including both large and small gate-channel. The lightly-doped n-drift region is modeled as a parasitic bipolar junction transistor (BJT) and diode which improves the accuracy of the model by exhibiting the quasi-saturation effect when compared to available BSIM models. Furthermore, this model can be incorporated to develop fault models for testing and diagnosis of high-voltage devices.