DocumentCode
2854159
Title
How can the results of silicon debug justify the investment in design-for- debug infrastructure?
Author
Gottlieb, B.
Author_Institution
Intel Corp., Santa Clara, CA
fYear
2007
fDate
21-26 Oct. 2007
Firstpage
1
Lastpage
1
Abstract
With the increase in clock domains and multi-core designs, the impact of adding traditional debug features is becoming prohibitive. The impact is mainly in restrictions in device operation and increased risk to the design itself. It is no longer a given that these features pay for themselves in terms of benefit to silicon debug and test.
Keywords
automatic test pattern generation; design for testability; elemental semiconductors; semiconductor device testing; silicon; Si; clock domains; design-for-debug infrastructure; multicore designs; silicon debuging; silicon test;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 2007. ITC 2007. IEEE International
Conference_Location
Santa Clara, CA
ISSN
1089-3539
Print_ISBN
978-1-4244-1127-6
Type
conf
DOI
10.1109/TEST.2007.4437678
Filename
4437678
Link To Document