Title :
Efficient area optimization for multi-level spiral floorplans
Author :
Chen, Cheng-Hsi ; Tollis, Ioannis G.
Author_Institution :
Dept. of Comput. Sci., Texas Univ., Dallas, Richardson, TX, USA
Abstract :
An algorithm for solving the area optimization problem for multilevel spiral/slicing floorplans is presented. It is shown that in the worst case, there are exponentially many useful implementations for a multilevel spiral floorplan. The reasons why this does not happen very often are also shown. The experimental data suggest that in most cases, the area optimization problem of multilevel spiral/slicing floorplans can be solved in O(n2 log n) time and O(n2) space, where n is the number of basic rectangles of the floorplans
Keywords :
VLSI; circuit layout CAD; modules; network routing; trees (mathematics); area optimization; basic rectangles; multi-level spiral floorplans; slicing floorplans; Circuit topology; Computer science; Joining processes; Optimization methods; Partitioning algorithms; Polynomials; Registers; Spirals; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1992. ISCAS '92. Proceedings., 1992 IEEE International Symposium on
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-0593-0
DOI :
10.1109/ISCAS.1992.230023
