• DocumentCode
    2854293
  • Title

    IC layout verification method, which considers mismatches between results of lithographical modeling and a real image

  • Author

    Koukharenko, S.N. ; Volk, S.V. ; Zayats, A.M. ; Smimov, A.G.

  • Author_Institution
    Belarusian State Univ. of Informatics & Radioelectron., Minsk
  • Volume
    2
  • fYear
    2005
  • fDate
    16-16 Sept. 2005
  • Firstpage
    455
  • Abstract
    This paper describes a method of IC layout verification on manufacturability. The method considers matches between results of lithography modeling and a image on a wafer obtained after manufacturing
  • Keywords
    integrated circuit layout; integrated circuit manufacture; lithography; IC layout verification method; lithography modeling; manufacturability; real image; Helium; Integrated circuit layout; Integrated circuit modeling; Manufacturing; Microwave technology; Tellurium;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Microwave & Telecommunication Technology, 2005 15th International Crimean Conference
  • Conference_Location
    Sevastopol, Crimea
  • Print_ISBN
    966-7968-80-4
  • Type

    conf

  • DOI
    10.1109/CRMICO.2005.1564989
  • Filename
    1564989
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2854293