Title :
Is a Protocol Aware test system feasible?
Author_Institution :
Teradyne Inc., North Reading, MA
Abstract :
A Protocol Aware (PA) test system would greatly assist the test engineer in multiple highly leveraged activities but is such a system in fact possible to build? One must construct the system so that pins can be grouped by membership in the various protocols on the DUT. Once grouped, local processing must be flexible enough to understand each protocol and respond properly to commands with reasonable latency. Since the supply of new protocols is unlimited, it must be possible to add new protocols at any time. And then, when all this is complete, it must be possible to synchronize operation of the various protocols so that a complete test of the DUT results.
Keywords :
DRAM chips; field programmable gate arrays; integrated circuit testing; logic testing; DDR2 DRAM; DUT; FPGA technology; chip memory; hardware design approach; high speed protocols; latency terms; pin electronics; protocol aware test system;
Conference_Titel :
Test Conference, 2007. ITC 2007. IEEE International
Conference_Location :
Santa Clara, CA
Print_ISBN :
978-1-4244-1127-6
DOI :
10.1109/TEST.2007.4437692
