Systematic derivation of the processing element of a systolic array based on residue number system

A systematic methodology for synthesizing optimal VLSI residue number system architectures using full adders (FAs) as the basic building block is introduced. The design methodology derives array architectures starting from the algorithmic level. Taking into account the target architecture, the proposed synthesis procedure derives a dependence graph of the algorithm using uniform recurrent equations, specifies the architecture topology, allocates, and schedules the computations within FAs. The derived architectures, called inner product step processors, can be used as the processing element of a regular array architecture. The design methodology derives FA-based implementations that completely eliminate the need for ROM-table look-up. The resulting architectures exhibit less hardware complexity and much higher throughput rates than ROM-based ones