• DocumentCode
    285465
  • Title

    Hierarchical residue numbering system suitable for VLSI arithmetic architectures

  • Author

    Yassine, H.M.

  • Author_Institution
    Dept. of Electr. Eng., Brunel Univ., Uxbridge, UK
  • Volume
    2
  • fYear
    1992
  • fDate
    10-13 May 1992
  • Firstpage
    811
  • Abstract
    The authors describe a novel residue number system called the hierarchical residue number system (HRNS). The proposed HRNS is based on representing the large moduli of a residue number system by residue number subsystems with smaller moduli. This process may be repeated if necessary until the moduli are very small (e.g. single digits). The proposed HRNS can realize large dynamic ranges with few distinct but small-value moduli. This feature simplifies the conversion from residue format to weighted representations
  • Keywords
    VLSI; digital arithmetic; microprocessor chips; DSP; VLSI arithmetic architectures; hierarchical RNS; residue number system; weighted representations; Arithmetic; Cathode ray tubes; Digital signal processing; Dynamic range; Error correction; Hardware; Redundancy; Signal design; Signal processing; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 1992. ISCAS '92. Proceedings., 1992 IEEE International Symposium on
  • Conference_Location
    San Diego, CA
  • Print_ISBN
    0-7803-0593-0
  • Type

    conf

  • DOI
    10.1109/ISCAS.1992.230098
  • Filename
    230098