The architecture and analysis of a hybrid number system processor

Author

Lai, F.S.

Author_Institution

IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA

Volume

2

fYear

1992

fDate

10-13 May 1992

Firstpage

803

Abstract

A hybrid number system processor is studied and analyzed. This processor uses the FLP (floating point) to LNS (logarithm number system) conversion algorithm to transform all the incoming 32-b floating-point numbers into 32-b logarithmic numbers. Arithmetic operations are performed in the LNS domain. The output FLP results are also obtained by using the LNS to FLP conversion algorithm. All the arithmetic operations including addition and subtraction can be implemented by using the anti-logarithm PLA (programmable logic array). Error analysis indicates that the Taylor series truncation leads to very small error when the ROM size is properly chosen for the desired precision. Consequently, the finite width truncation becomes the major source of conversion errors

Keywords

computer architecture; digital arithmetic; error analysis; LNS to FLP conversion algorithm; ROM size; Taylor series truncation; antilogarithm PLA; conversion errors; floating point; hybrid number system processor; logarithm number system; programmable logic array; Difference equations; Differential equations; Finite difference methods; Hardware; Programmable logic arrays; Read only memory; Silicon; Table lookup; Taylor series;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1992. ISCAS '92. Proceedings., 1992 IEEE International Symposium on

Conference_Location

San Diego, CA

Print_ISBN

0-7803-0593-0

Type

conf

DOI

10.1109/ISCAS.1992.230100

Filename

230100