Title :
Layout-driven test generation
Author :
Nigh, P. ; Maly, W.
Author_Institution :
Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA
Abstract :
Conventionally, test vectors are generated using gate-level models to represent the circuit design and abstract fault models (e.g. the stuck-fault model) to describe all of the processing defects causing circuit failure. The authors demonstrate that test vectors can be generated using realistic defect models and actual IC layouts, which should lead to test vectors with a higher defect detectability. The layout-driven generation of the faults has a computational complexity which is similar to that of design-rule checking, i.e. O(n log n).<>
Keywords :
automatic testing; circuit layout CAD; fault location; integrated logic circuits; logic testing; IC layouts; automatic testing; defect detectability; defect models; design-rule checking; layout driven test generation; test vectors; Circuit faults; Circuit synthesis; Circuit testing; Computational complexity; Current measurement; Integrated circuit layout; Integrated circuit modeling; Integrated circuit testing; Power measurement; Semiconductor device modeling;
Conference_Titel :
Computer-Aided Design, 1989. ICCAD-89. Digest of Technical Papers., 1989 IEEE International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-1986-4
DOI :
10.1109/ICCAD.1989.76925
