DocumentCode
285480
Title
A novel self-calibrating scheme for video-rate 2-step flash analog-to-digital converter
Author
Gu, Zhiqiang ; Snelgrove, W. Martin
Author_Institution
Dept. of Electr. Eng., Toronto Univ., Ont., Canada
Volume
2
fYear
1992
fDate
10-13 May 1992
Firstpage
601
Abstract
The authors present an online trimming technique and an error-code self-trimming algorithm for video rate 2-step flash analog-to-digital converters (ADCs). The self-calibrating scheme, combining a digital error correction process and the self-trimming algorithm, dynamically maintains the random offsets of the comparators well within ±0.6 LSB and counteracts the interstage gain error, while improving the design of a conventional 2-step ADC towards a higher speed, a smaller size, and a lower power dissipation. The technique is applicable to subranging ADCs of up to any accuracy. Results from simulation of a 10-bit ADC are given to illustrate the superior efficiency of the scheme and the simplicity of the corresponding circuitry
Keywords
analogue-digital conversion; calibration; error correction; 10-bit ADC; A/D convertor; comparators; digital error correction; error-code self-trimming algorithm; interstage gain error; online trimming technique; random offsets; self-calibrating scheme; subranging ADCs; two-step flash ADC; video-rate; Algorithm design and analysis; Analog-digital conversion; CMOS technology; Circuit simulation; Error correction; Heuristic algorithms; Linearity; Power dissipation; Probability density function; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1992. ISCAS '92. Proceedings., 1992 IEEE International Symposium on
Conference_Location
San Diego, CA
Print_ISBN
0-7803-0593-0
Type
conf
DOI
10.1109/ISCAS.1992.230120
Filename
230120
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