DocumentCode
2855017
Title
Computation of bus current variance for reliability estimation of VLSI circuits
Author
Najm, F. ; Hajj, I. ; Yang, P.
Author_Institution
Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
fYear
1989
fDate
5-9 Nov. 1989
Firstpage
202
Lastpage
205
Abstract
A novel technique for deriving the variance waveform for CMOS circuits is presented. Using this technique, the authors establish the importance of the variance waveform by showing that its contribution to the mean-time-to-failure estimate can be in the range of 100% to 200% relative to that of the expected waveform. The technique has been built into the probabilistic simulator CREST and has shown good agreement with SPICE, as well as excellent speedup.<>
Keywords
CMOS integrated circuits; VLSI; digital simulation; electronic engineering computing; probability; reliability; waveform analysis; CMOS circuits; CREST; VLSI circuits; bus current variance; mean-time-to-failure estimate; probabilistic simulator; reliability estimation; variance waveform; Circuit simulation; Electromigration; Instruments; Laboratories; Persistent currents; SPICE; Semiconductor device modeling; Stochastic processes; Stress; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer-Aided Design, 1989. ICCAD-89. Digest of Technical Papers., 1989 IEEE International Conference on
Conference_Location
Santa Clara, CA, USA
Print_ISBN
0-8186-1986-4
Type
conf
DOI
10.1109/ICCAD.1989.76936
Filename
76936
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