• DocumentCode
    285506
  • Title

    A new efficient systolic architecture for the 2D discrete Fourier transform

  • Author

    Chen, Chang-Yu ; Wang, Chin-Liang

  • Author_Institution
    Inst. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan
  • Volume
    2
  • fYear
    1992
  • fDate
    10-13 May 1992
  • Firstpage
    689
  • Abstract
    Proposes a 2D systolic array for performing the 2D N×N-point discrete Fourier transform (DFT). This array is constructed based on the use of the Goertzel algorithm to realize the 2-D DFT in a row-column-wise or column-row-wise format. Unlike the conventional row-column decomposition method, the proposed system involves no matrix transposition problems. In addition, the system possesses the features of regularity, modularity, and concurrency. As a consequence, it is well suited to VLSI implementation and has a very high throughput of one 2-D transition per N cycles. Moreover, the utilization efficiency of the proposed system is 100%, and the latency (processing time for a single 2-D transform) is 4 N-1 cycles. In terms of the area-time complexity, the proposed approach is a fast design and reaches the lower bound
  • Keywords
    VLSI; fast Fourier transforms; parallel algorithms; systolic arrays; 2D discrete Fourier transform; Goertzel algorithm; VLSI; area-time complexity; column-row-wise format; concurrency; latency; modularity; regularity; row-column-wise format; systolic architecture; utilization efficiency; Circuits; Concurrent computing; Delay; Discrete Fourier transforms; Equations; Signal processing algorithms; Systolic arrays; Throughput; Two dimensional displays; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 1992. ISCAS '92. Proceedings., 1992 IEEE International Symposium on
  • Conference_Location
    San Diego, CA
  • Print_ISBN
    0-7803-0593-0
  • Type

    conf

  • DOI
    10.1109/ISCAS.1992.230158
  • Filename
    230158