• DocumentCode
    285508
  • Title

    The concepts of COMPAR- a compiler for massively parallel architectures

  • Author

    Arzt, U. ; Teich, J. ; Thiele, L.

  • Author_Institution
    Inst. of Microelectron., Saarland Univ., Saarbrucken, Germany
  • Volume
    2
  • fYear
    1992
  • fDate
    10-13 May 1992
  • Firstpage
    681
  • Abstract
    Describes the concepts of a compiler for mapping programs onto massively parallel architectures, e.g. VLSI signal processing arrays, and general-purpose-type massively parallel architectures, e.g. digital signal processors. The input to the system is a single-assignment code. Using a transformative approach, the initial program is refined using provably correct program transformations in order to solve typical mapping problems. These are the localization of global data dependencies, the scheduling of computations in time and space, the generation of control, and the matching of resource constraints. After application of the architecture-independent transformation tools, a back end consisting of architecture-dependent generators creates output code from the transformed program. Thus, architecture-independent design of parallel programs is possible. The main concepts of the COMPAR design system are described. The software instances of the implementation are modeled, and the class of input programs is formally introduced. The design flow is explained by introducing the required program transformations. The main advantages of the system in comparison to similar design systems are outlined
  • Keywords
    VLSI; digital signal processing chips; parallel architectures; program compilers; resource allocation; scheduling; COMPAR; VLSI signal processing arrays; architecture-independent transformation tools; compiler; design flow; digital signal processors; global data dependencies; massively parallel architectures; provably correct program transformations; resource constraints; scheduling; single-assignment code; Aerospace electronics; Algorithm design and analysis; Array signal processing; Computer architecture; Parallel architectures; Parallel processing; Pipeline processing; Program processors; Signal processing algorithms; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 1992. ISCAS '92. Proceedings., 1992 IEEE International Symposium on
  • Conference_Location
    San Diego, CA
  • Print_ISBN
    0-7803-0593-0
  • Type

    conf

  • DOI
    10.1109/ISCAS.1992.230160
  • Filename
    230160