A massively parallel and highly pipelined VLSI analog neocognitron image processor

An efficient way to implement a neocognitron system is presented. The computation at each processing element (neuron) is more complicated than in the other conventional neural network models. Its three-dimensional structure requires a large number of neurons (more than 34000 for Fukushima´s example consisting of a 19×19 pixel input) and complicated wire connections between them. In the present study, these problems are overcome by a combination of efficient analog basic cells and digital techniques (a systolic array which consists of analog circuits). To test the feasibility of the proposed approach, a sample chip of an element of this system was fabricated by MOSIS and tested. Concurrently, a simulation program was also developed to simulate and verify the whole system performance. With the proposed small neuron model, it is possible to implement the whole neocognitron system applicable to actual application in one chip, or a few chips using the state-of-the-art technology