DocumentCode
285530
Title
A refreshable multilevel memory for a continuous-time synapse
Author
Hasler, Paul ; Akers, Lex
Author_Institution
Center for Solid State Electron. Res., Arizona State Univ., Tempe, AZ, USA
Volume
3
fYear
1992
fDate
10-13 May 1992
Firstpage
1561
Abstract
Multilevel dynamic storage employing refreshing schemes potentially allows very compact synapses with fast read and write operations. A circuit implementation is described which performs an 8-b to 10-b transmission of dynamically stored value and a 2-MHz, successive approximation, A/D→D/A (analog-to-digital→digital-to-analog) conversion. The synapse size is 105 μm×75 μm for a 2-μm process. This implementation is capable of bandwidths in the low megahertz (1 to 20 MHz)
Keywords
analogue storage; feedforward neural nets; random-access storage; 1 to 20 MHz; 2 MHz; 2 micron; A/D to D/A conversion; circuit implementation; continuous-time synapse; dynamically stored value; refreshable multilevel memory; refreshing schemes; successive approximation; synapse size; synapses; Bandwidth; Capacitors; Circuits; Lead; Low voltage; Neural networks; Pulse amplifiers; Random access memory; Signal restoration; Transistors;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1992. ISCAS '92. Proceedings., 1992 IEEE International Symposium on
Conference_Location
San Diego, CA
Print_ISBN
0-7803-0593-0
Type
conf
DOI
10.1109/ISCAS.1992.230200
Filename
230200
Link To Document