A hybrid architecture for feed-forward multi-layer neural networks

The building blocks of this architecture are mostly in analog CMOS to reduce the number of interconnecting wires. The memory, where the weights are stored, is implemented digitally to avoid the reliability and long-term preservation problems associated with the current analog storage schemes. The discrete nature of digital weights does not produce any problem in the application considered here, since the weights are pretrained. The number of connections to any layer is reduced to the same number as the neurons in the preceding layer without any loss in generality. The building blocks have been fabricated and tested. A proof-of-concept chip has also been designed in a double metal, single polysilicon, p-well CMOS process. With modest clocking speeds, the circuit will have latency times on the order of microseconds for practical problems