Title :
Interconnection network switch design for parallel DSP systems
Author :
Fujii, Tetsurou ; Ono, Sadayasu
Author_Institution :
NTT Transmission Syst. Lab., Yokosuka, Japan
Abstract :
Describes the design of an interconnection network switch VLSI for parallel digital signal processing (DSP) systems. This VLSI features 6×400 Mb/s bidirectional communication ports and 1.44-Gb/s internal switching capability for realizing efficient packet-switched communication among many processing elements. To achieve this performance with existing CMOS technology, the transport line transfers 8 b in parallel at 50 MHz; input data are first multiplexed up to 64 b and switched at 25 MHz. An automatic routing function is implemented on each switch using a distributed routing table scheme. A high-level behavioral description based CAD (computer-aided design) system called PARTHENON is used to design the functions and logic circuits of this VLSI. The suitability and effectiveness of PARTHENON for switch design are also shown in terms of parallel operation and finite state machine design
Keywords :
CMOS integrated circuits; VLSI; circuit layout CAD; image processing; logic CAD; packet switching; parallel processing; 144 Gbits/s; 25 MHz; 400 Mbits/s; 50 MHz; CAD; CMOS technology; PARTHENON; VLSI; automatic routing function; behavioral description; bidirectional communication ports; distributed routing table scheme; finite state machine; interconnection network switch, image processing; internal switching capability; logic circuits; packet-switched communication; parallel DSP systems; Bidirectional control; CMOS technology; Communication switching; Design automation; Digital signal processing; Multiprocessor interconnection networks; Routing; Signal design; Switches; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1992. ISCAS '92. Proceedings., 1992 IEEE International Symposium on
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-0593-0
DOI :
10.1109/ISCAS.1992.230211
