Fast incremental netlist compilation of hierarchical schematics

Fast incremental techniques for maintaining and quickly updating the net list underlying a hierarchical schematic design are presented. For most user modifications the net list can be incrementally updated in a fraction of the time required using batch compilation techniques, often with no perceivable delay to the user. As a side result, the incremental net list compiler yields a list of affected electrical nodes that can be used to guide an incremental simulator which resimulates only the affected region of the circuit.<>