DocumentCode :
2855435
Title :
Structure optimization in logic schematic generation
Author :
Lee, T.D. ; McNamee, L.P.
Author_Institution :
Dept. of Comput. Sci., California Univ., Los Angeles, CA, USA
fYear :
1989
fDate :
5-9 Nov. 1989
Firstpage :
330
Lastpage :
333
Abstract :
An approach is presented for generating structurally near-optimal logic schematic diagrams from net lists. Unlike previous methods, preprocessing is performed to globally reduce the structural complexity of the anticipated schematic topology before the extraction of structural clusters. Since the optimized circuit topology may still be nonplanar, a novel weighted crossover resolution method is applied to temporarily remove costly local nets to extract important structural clusters and aligned nets in the planarized topology. A grid is assigned so that placement and global routing of the logic schematics can be generated with the desired topology that includes well-formed structural clusters.<>
Keywords :
circuit layout CAD; logic CAD; optimisation; aligned nets; global routing; logic schematic generation; near-optimal logic schematic diagrams; net lists; optimized circuit topology; placement; planarized topology; preprocessing; structural clusters; structural complexity; structure optimisation; weighted crossover resolution method; Circuit topology; Computer science; Feedback loop; Humans; Logic gates; Mesh generation; Optimization methods; Routing; Signal design; Signal generators;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer-Aided Design, 1989. ICCAD-89. Digest of Technical Papers., 1989 IEEE International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-1986-4
Type :
conf
DOI :
10.1109/ICCAD.1989.76964
Filename :
76964
Link To Document :
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