Title :
A high-speed architecture for ADPCM codec
Author :
Shanbhag, Naresh R. ; Parhi, Keshab K.
Author_Institution :
Dept. of Electr. Eng., Minnesota Univ., Minneapolis, MN, USA
Abstract :
A pipelined architecture for adaptive pulse code modulation (ADPCM) is presented. The architecture is developed by the application of a realized form of look-ahead. The hardware overhead is only the pipelining latches and is independent of the number of quantizer levels, the predictor order, and the pipelining level. The codec latency is smaller than the level of pipelining. Under the assumption of small quantization error, the convergence properties of the pipelined architecture are compared with those of the serial one. Speech and image coding examples are presented to support the conclusions reached
Keywords :
codecs; image coding; parallel architectures; pipeline processing; pulse-code modulation; speech analysis and processing; ADPCM codec; adaptive pulse code modulation; codec latency; convergence properties; hardware overhead; image coding; look-ahead; pipelined architecture; pipelining level; predictor order; quantization error; quantizer levels; speech coding; Codecs; Convergence; Delay; Hardware; Image coding; Modulation coding; Pipeline processing; Pulse modulation; Quantization; Speech coding;
Conference_Titel :
Circuits and Systems, 1992. ISCAS '92. Proceedings., 1992 IEEE International Symposium on
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-0593-0
DOI :
10.1109/ISCAS.1992.230216
