An optimal transistor-chaining algorithm for CMOS cell layout

Author

Chi-Yi Hwang ; Yung-Ching Hsieh ; Youn-Long Lin ; Yu-Chin Hsu

Author_Institution

Dept. of Comput. Sci., Tsing Hua Univ., Hsinchu, Taiwan

fYear

1989

fDate

5-9 Nov. 1989

Firstpage

344

Lastpage

347

Abstract

A fast algorithm is produced for the optimal transistor chaining problem in CMOS functional cell layout based on T. Uehara and W.M. van Cleemput´s layout style (IEEE Trans. Comput., vol. C-30, p.305-12, May 1981). The algorithm takes a transistor-level circuit schematic and outputs a minimum set of chains. Possible diffusion abutments between the transistor pairs are modeled as a bipartite graph. A depth-first search algorithm is used to search for the optimal chaining. Theorems on the number of branches needed to be explored at each node of the search tree are derived. A theoretical lower bound on the size of the chain set is derived. This bound enables pruning the search tree efficiently. The algorithm has been implemented and tested. It is able to find optimal solutions almost instantly for all the cases available to use from the literature.<>

Keywords

CMOS integrated circuits; circuit layout CAD; computational complexity; search problems; CMOS cell layout; CMOS functional cell layout; bipartite graph; depth-first search algorithm; lower bound; optimal transistor-chaining algorithm; pruning; search tree; Bipartite graph; CMOS technology; Circuits; Computer science; Semiconductor device modeling; Strips; Testing; Tree graphs; Upper bound; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer-Aided Design, 1989. ICCAD-89. Digest of Technical Papers., 1989 IEEE International Conference on

Conference_Location

Santa Clara, CA, USA

Print_ISBN

0-8186-1986-4

Type

conf

DOI

10.1109/ICCAD.1989.76967

Filename

76967