Controlled-load limited switch dynamic logic circuit

Author

Sivagnaname, Jayakumaran ; Ngo, Hung C. ; Nowka, Kevin J. ; Montoye, Robert K. ; Brown, Richard B.

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA

fYear

2005

fDate

21-23 March 2005

Firstpage

83

Lastpage

87

Abstract

Limited switch dynamic logic (LSDL), a high performance logic circuit, has been modified by introducing a pseudo-nMOS style load. The resultant circuit consumes less power, primarily due to the reduction of capacitance on the clock network. The controlled-load LSDL is shown to be more robust to noise and power rail bounce. A 64-bit rotator circuit was used in the analysis. The effect of process variation on circuit performance is also evaluated.

Keywords

capacitance; integrated circuit design; logic circuits; microprocessor chips; power consumption; random noise; capacitance reduction; clock network; controlled-load limited switch dynamic logic circuit; high performance designs; microprocessor; noise; power consumption; power rail bounce; pseudo-nMOS style load; rotator circuit; Capacitance; Circuit noise; Circuit optimization; Clocks; Logic circuits; Noise robustness; Rails; Robust control; Switches; Switching circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Quality of Electronic Design, 2005. ISQED 2005. Sixth International Symposium on

Print_ISBN

0-7695-2301-3

Type

conf

DOI

10.1109/ISQED.2005.35

Filename

1410562