• DocumentCode
    2855653
  • Title

    Interconnection length estimation for optimized standard cell layouts

  • Author

    Pedram, M. ; Preas, B.

  • Author_Institution
    Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
  • fYear
    1989
  • fDate
    5-9 Nov. 1989
  • Firstpage
    390
  • Lastpage
    393
  • Abstract
    An accurate model for the prediction of interconnection lengths for standard cell layouts is presented. On the designs in the test suite estimates are within 10% of the actual layouts. The model abstracts the important features of placement, global routing, and channel routing. The predicted results are obtained from analysis of the net list. No prior knowledge of the functionality of the design is used. Accurate prediction of the interconnection length is useful for estimating the actual layout area, for evaluating the fit of a logic design to a fabrication technology, and for solving placement and routing algorithms.<>
  • Keywords
    VLSI; circuit layout CAD; logic CAD; optimisation; channel routing; fabrication technology; global routing; interconnection length estimation; layout area; logic design; net list; optimized standard cell layouts; placement; Computer science; Curve fitting; Integrated circuit interconnections; Laboratories; Logic design; Predictive models; Process design; Routing; Wire; Wiring;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer-Aided Design, 1989. ICCAD-89. Digest of Technical Papers., 1989 IEEE International Conference on
  • Conference_Location
    Santa Clara, CA, USA
  • Print_ISBN
    0-8186-1986-4
  • Type

    conf

  • DOI
    10.1109/ICCAD.1989.76976
  • Filename
    76976