Title :
Redundancy identification and removal in combinational logic circuits
Author :
Lee, Tien-Chien ; Jha, Niraj K.
Author_Institution :
Dept. of Electr. Eng., Princeton Univ., NJ, USA
Abstract :
The authors present an efficient RI and RR (redundancy identification and removal) method for combinational logic circuits, called RIDAR, which can perform RI by taking advantage of the functional specification and can remove simultaneously more than one redundancy during one RR iteration. Experimental results show that significant savings in literal-count can be obtained for synthesized circuits in small amounts of CPU time. Surprisingly, it is found that a significant reduction in literal-count can be obtained in many cases for combinational circuits even when conventional ATPG (automatic test pattern generation) declares the circuit to be irredundant
Keywords :
combinatorial circuits; identification; logic design; logic testing; redundancy; RIDAR; combinational logic circuits; redundancy identification; Automatic test pattern generation; Central Processing Unit; Circuit faults; Circuit synthesis; Circuit testing; Combinational circuits; Delay; Logic circuits; Logic testing; Redundancy;
Conference_Titel :
Circuits and Systems, 1992. ISCAS '92. Proceedings., 1992 IEEE International Symposium on
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-0593-0
DOI :
10.1109/ISCAS.1992.230282
