Acceleration of fault propagation trace-based fault simulation of combinational circuits

Significant improvements in the speed of fault simulation of combinational circuits have been achieved by parallel pattern implementations of trace-based methods for identifying detected faults. The authors present methods of achieving further speed improvements by reducing explicit fault simulation of stem faults. The method presented here reduces fault propagation in trace-based parallel-pattern simulation. The concept of joining stems is introduced and shown to be effective in reducing simulation time even if fault-dropping is not used. It is shown that the method proposed can be combined effectively with the quit-line method proposed earlier. Results of simulating the ISCAS85 benchmark combinational circuits with the proposed methods indicate that they are faster than other published methods, both with and without fault-dropping