Highly modular and concurrent 2-D DCT chip

A novel algorithm and architecture for a class of 2-D block transforms such as the 2-D discrete cosine transform (DCT) have been developed. The proposed approach allows fast computation by (1) overlapped transformations of row and column data, (2) eliminating the explicit transpose operations, and (3) modular and easily pipelinable structure. Using the proposed approach, a 2-D DCT chip has been designed which has a highly modular structure and concurrent operations. The total computation time is significantly reduced compared to previous approaches. This architecture is suitable for high-speed applications such as HDTV (high-definition television) due to easy pipelining and simple control. The approach can be extended to N-D transforms