DocumentCode :
285605
Title :
A VLSI filter architecture for digital HDTV codecs
Author :
Kowalczuk, J. ; Ebrahimi, T. ; Mlynek, D. ; Kunt, M.
Author_Institution :
Swiss Federal Inst. of Technol., Laussane, Switzerland
Volume :
3
fYear :
1992
fDate :
10-13 May 1992
Firstpage :
1077
Abstract :
The authors describe a compact VLSI implementation of fast pipelined two-dimensional FIR filters. A polyphase architecture is presented. The filter bank makes special use of coefficients which are in powers-of-two. This leads to an interest scheme where only shift and add operations are compared. A novel design strategy has been used to speed up the algorithm, as well as a novel adder. Internally, the speed achieved is around 200 MHz
Keywords :
CMOS integrated circuits; VLSI; codecs; digital communication systems; high definition television; pipeline processing; television equipment; two-dimensional digital filters; video signals; 200 MHz; 2D filter bank; VLSI filter architecture; adder; design strategy; digital HDTV codecs; polyphase architecture; two-dimensional FIR filters; Channel bank filters; Codecs; Digital filters; Filter bank; Finite impulse response filter; Gabor filters; HDTV; Image coding; Low pass filters; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 1992. ISCAS '92. Proceedings., 1992 IEEE International Symposium on
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-0593-0
Type :
conf
DOI :
10.1109/ISCAS.1992.230293
Filename :
230293
Link To Document :
بازگشت