High sample rate systolic architectures for median filters

The author presents high-sample-rate systolic architectures for computing one-dimensional median filters. Two configurations are studied: one in which the samples are stored in order of arrival and one in which the samples are stored in sorted order. The architecture for both cases consists of a linear systolic array of processors. The computations in each processors are pipelined in order to achieve high sample rates. For instance, the sample rate is increased by a factor of 2 (compared to existing architectures) by performing comparisons of elements in window W_i and rank updates (in the first configuration) or sorting (in the second configuration) of elements in window W_i-1 simultaneously