Title :
Reduced test application time based on reachability analysis
Author :
Hanioitakis, T. ; Tragoudas, S. ; Pani, G.
Author_Institution :
Electr. & Comput. Eng. Dept, Southern Illinois Univ., Carbondale, IL, USA
Abstract :
A test application method to reduce the test application time in full scan designs is presented. It can be used either during or after the test pattern generation phase so that one or more patterns can be reached from an already scanned pattern using scan reapply or scan shift operations. The presented approach is based on established methods for reachability analysis in sequential verification and a fault grading algorithm to ensure that all targeted faults are covered.
Keywords :
automatic test pattern generation; logic testing; reachability analysis; fault grading algorithm; full scan designs; reachability analysis; reduced test application time; scan reapply; scan shift; sequential verification; test pattern generation; Application software; Automatic test pattern generation; Automatic testing; Boolean functions; Clocks; Data structures; Delay; Design engineering; Reachability analysis; Test pattern generators;
Conference_Titel :
Quality of Electronic Design, 2005. ISQED 2005. Sixth International Symposium on
Print_ISBN :
0-7695-2301-3
DOI :
10.1109/ISQED.2005.102
