DocumentCode :
2856201
Title :
Dynamic test compaction for bridging faults
Author :
Pomeranz, Irith ; Reddy, Sudhakar M.
Author_Institution :
Sch. of Electr. & Comput. Eng, Purdue Univ., West Lafayette, IN, USA
fYear :
2005
fDate :
21-23 March 2005
Firstpage :
250
Lastpage :
255
Abstract :
We describe a dynamic test compaction procedure for four-way bridging faults. Under this fault model, a pair of lines gi, gj is associated with four bridging faults corresponding to two possible combinations of opposite values on gi and gj, and two options for the line whose value is faulty in the presence of the fault (either gi or gj). Compaction is achieved by simultaneously considering faults that have a line gi with a value αi in common, such that the value αi on gi is affected by the presence of the fault. Faults with a common line gi and value αi differ only in the second line gj of each pair of bridged lines, and the second lines only need to be assigned the value α~i in order to detect all the faults. This strong relationship between the faults allows us to derive tests that detect large numbers of these faults, resulting in compact test sets.
Keywords :
fault simulation; logic testing; compact test sets; dynamic test compaction; fault model; four-way bridging faults; full-scan circuits; Circuit faults; Circuit testing; Cities and towns; Compaction; Delay; Electrical fault detection; Fault detection; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Quality of Electronic Design, 2005. ISQED 2005. Sixth International Symposium on
Print_ISBN :
0-7695-2301-3
Type :
conf
DOI :
10.1109/ISQED.2005.48
Filename :
1410592
Link To Document :
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