Symbolic synthesis as a tool for circuit optimization

To cover a class of various analog design problems the authors propose an approach based on a concept of open modular tools. Design tasks are decomposed into modular entities and common modules identified. In order to minimize development effort both in the case of programs dedicated to standard design problems and in the case of specific applications, interface standardization is proposed. The design topics presented are characterized either by repetitive analyses at fixed topology or by the necessity of topology adaptation as a function of design specifications. In both cases interfacing with a symbolic simulator is proposed: in the first case as a possible reduction of computational effort and in the second case as an element of a more general strategy of topological synthesis