DocumentCode :
2856292
Title :
Parametric yield analysis and constrained-based supply voltage optimization
Author :
Rao, Rahul ; Agarwal, Kanak ; Devgan, Anirudh ; Nowka, Kevin ; Sylvester, Dennis ; Brown, Richard
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
fYear :
2005
fDate :
21-23 March 2005
Firstpage :
284
Lastpage :
290
Abstract :
Parametric yield loss has become a serious concern in leakage dominated technologies. We discuss the impact of leakage on parametric yield and show that leakage can cause yield windows to shrink by imposing a two-sided constraint on the window. We present a mathematical framework for yield estimation under device process variation for given power and frequency constraints. The model is validated against Monte Carlo simulations for an industry process and is shown to have typical error of less than 5%. We then demonstrate the importance of optimal supply voltage selection for yield maximization. We also investigate the sensitivity of parametric yield to applied frequency and power constraints. Finally, we apply the proposed framework to the problem of maximizing the shipping frequency in the presence of given yield and power constraints.
Keywords :
electric potential; integrated circuit yield; optimisation; parameter estimation; constraint-based supply voltage optimization; device process variation; frequency constraints; integrated circuits; leakage dominated technologies; nanometer regime; parametric yield analysis; power constraints; shipping frequency; yield estimation; yield maximization; Cities and towns; Constraint optimization; Educational institutions; Energy consumption; Frequency estimation; Laboratories; Manufacturing processes; Power generation; Threshold voltage; Yield estimation;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Quality of Electronic Design, 2005. ISQED 2005. Sixth International Symposium on
Print_ISBN :
0-7695-2301-3
Type :
conf
DOI :
10.1109/ISQED.2005.90
Filename :
1410597
Link To Document :
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