An ASIC architecture for real-time image/video coding based on fixed-basis-distortion vector quantization

An application-specific-IC (ASIC) architecture for real-time video signal processing is presented. The authors present some optimization tasks at the algorithm level by taking into account computation and memory requirements to ensure that an optimal solution can be achieved. In the architecture design, a distributed arithmetic technique replacing the traditional amplifier, is exploited to perform energy computation. By exploiting pipelining and parallelism, required computations can be realized through a very regular structure. The results show that a single chip containing 128 code vectors can be achieved for multistage or full search vector quantization coding with reasonable area and input/output pin-count