A codesign tool to validate and improve an FPGA based test strategy for high resolution audio ADC

Results from intensive investigation of a new so-called polynomial fitting method have demonstrated to be a promising technique for fast test of high-resolution ADC. Within this work, a recently developed CodeSimulink HW/SW codesign tool suitable to design, simulate and tune the digital HW required for the proposed method has been employed. The investigations have underlined the limits of the method and also allowed the introduction of possible improvements on the original technique, as shown in the paper.