• DocumentCode
    2856970
  • Title

    Modeling within-die spatial correlation effects for process-design co-optimization

  • Author

    Friedberg, Paul ; Cao, Yu ; Cain, Jason ; Wang, Ruth ; Rabaey, Jan ; Spanos, Costas

  • Author_Institution
    Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
  • fYear
    2005
  • fDate
    21-23 March 2005
  • Firstpage
    516
  • Lastpage
    521
  • Abstract
    Within-die spatial correlation of device parameter values caused by manufacturing variations has a significant impact on circuit performance. Based on experimental and simulation results, we: (1) characterize the spatial correlation of gate length over a full-field range of horizontal and vertical separation; (2) develop a rudimentary spatial correlation model; and (3) investigate its impact an the variability of circuit performance.
  • Keywords
    circuit optimisation; integrated circuit design; integrated circuit yield; nanoelectronics; circuit performance; device parameter values; gate length; manufacturing variations; nanoscale circuits; process-design co-optimization; within-die spatial correlation effects; Circuit optimization; Circuit simulation; Electric variables measurement; Electrical resistance measurement; Length measurement; Lithography; Manufacturing processes; Metrology; Robustness; Size measurement;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Quality of Electronic Design, 2005. ISQED 2005. Sixth International Symposium on
  • Print_ISBN
    0-7695-2301-3
  • Type

    conf

  • DOI
    10.1109/ISQED.2005.82
  • Filename
    1410637
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2856970