Automatic layout generation for digital BiCMOS cells

A digital BiCMOS cell generator that produces geometrical cell layout with electrically high performance is presented. The generator is based on a 4-row model in which p-MOSFETs and n-MOSFETs are laid on two middle rows and bipolar devices are laid on the top and bottom rows. The main operations involved in the generator include: (1) formation of MOS rows; (2) formation of bipolar device rows; (3) global routing; (4) routing over devices; and (5) channel routing. The generator handles typical constraints governing the placement and routing, such as area/shape, device matching, and routability constraints, as well as the constraints on timing delay for high speed circuits and user-specified I/O ports positions. The generator is linked to ChipGraph, an IC layout editor developed by Mentor Graphics, so that the designer can edit the resulting layout if necessary, and get the mask data in either GDS II or MCIF format for chip manufacture. The experimental results on several BiCMOS circuits are presented