Aging mechanisms in strained Si/high-k based pMOS transistors. Implications in CMOS circuits

Channel Hot Carrier (CHC) and Negative Bias Temperature Instability (NBTI) degradation has been studied in pMOSFETs with and without channel strain. The results show larger CHC degradation and a neglegible influence of NBTI on strained pMOS devices. The degradation effects are modeled to be introduced in a circuit simulator. The simulations of a CMOS inverter, which has been chosen as example circuit, show that degradation shifts the Voltage Transfer Characteristic (VTC). This effect is higher in strained devices. Concerning to the circuit speed and power consumption, the best initial performance of circuits designed with strained devices compensates their larger degradation.