DocumentCode
2857372
Title
A fast error correction technique for matrix multiplication algorithms
Author
Argyrides, C. ; Lisboa, C.A.L. ; Pradhan, D.K. ; Carro, L.
Author_Institution
Dept. of Comput. Sci., Univ. of Bristol, Bristol, UK
fYear
2009
fDate
24-26 June 2009
Firstpage
133
Lastpage
137
Abstract
Temporal redundancy techniques will no longer be able to cope with radiation induced soft errors in technologies beyond the 45 nm node, because transients will last longer than the cycle time of circuits. The use of spatial redundancy techniques will also be precluded, due to their intrinsic high power and area overheads. The use of algorithm level techniques to detect and correct errors with low cost has been proposed in previous works, using a matrix multiplication algorithm as the case study. In this paper, a new approach to deal with this problem is proposed, in which the time required to recompute the erroneous element when an error is detected is minimized.
Keywords
embedded systems; error correction; fault tolerant computing; matrix multiplication; fast error correction technique; matrix multiplication algorithms; radiation induced soft errors; single event transients; spatial redundancy techniques; temporal redundancy techniques; CMOS logic circuits; CMOS technology; Costs; Error correction; Fault tolerance; Logic devices; Pulse circuits; Redundancy; Space vector pulse width modulation; Voltage; fault tolerant algorithms; fault tolerant software execution; recomputation time; software fault tolerance;
fLanguage
English
Publisher
ieee
Conference_Titel
On-Line Testing Symposium, 2009. IOLTS 2009. 15th IEEE International
Conference_Location
Sesimbra, Lisbon
Print_ISBN
978-1-4244-4596-7
Electronic_ISBN
978-1-4244-4595-0
Type
conf
DOI
10.1109/IOLTS.2009.5195995
Filename
5195995
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