Title :
Pass-transistors pMOS based 8T SRAM cell for layout compaction
Author :
Bota, Sebastià A. ; Alorda, Bartomeu ; Torrens, Gabriel ; Segura, Jaume
Author_Institution :
Electron. Syst. Group, Univ. de les Illes Balears (UIB), Palma de Mallorca, Spain
Abstract :
We present a new 8-transistor (8T) SRAM cell design that uses pMOS devices as cell pass transistors controlled by the write word-line signal. The main advantage of this schema is the composition of a balanced 8T SRAM cell having four nMOS and four pMOS transistor that enables a more compact layout and area reduction. An exhaustive analysis about the impact on key parameters such as leakage consumption, write and read stability margins, read delay time and single event upsets for the new cell is reported. A trade-off between cell area reduction and write noise margin improvement is observed, while the remaining parameters are not impacted.
Keywords :
MOSFET; SRAM chips; circuit stability; integrated circuit layout; integrated circuit noise; leakage currents; 8T SRAM cell design; cell area reduction; cell pass transistor; layout compaction; leakage consumption; nMOS transistor; pass-transistor pMOS device; read delay time; single event upset; write noise margin; write word-line signal; write-and-read stability margin; CMOS integrated circuits; CMOS technology; Layout; MOSFETs; Random access memory; Static noise margin; Static-random-access-memory (SRAM); reliability; variation; write margin;
Conference_Titel :
Electron Devices (CDE), 2011 Spanish Conference on
Conference_Location :
Palma de Mallorca
Print_ISBN :
978-1-4244-7863-7
DOI :
10.1109/SCED.2011.5744184