DocumentCode
2857646
Title
Power-Aware Register Renaming in High-Performance Processors Power-Aware Register Renaming in High-Performance Processors
Author
Ayala, José L. ; López-Vallejo, Marisa ; Veidenbaum, Alexander
Author_Institution
Dept. de Ingenieria Electron., Univ. Politecnica de Madrid
fYear
2004
fDate
12-14 Jan. 2004
Firstpage
20
Lastpage
27
Abstract
This work presents an efficient multi-banked architecture of the register file, and a low-power compiler support which reduces energy consumption in this device by more than a 78%. The key idea of this work is based on a quasi-deterministic interpretation of the register assignment task, and the use of the voltage scaling techniques
Keywords
low-power electronics; parallel architectures; program compilers; high-performance processors; low-power compiler support; multibanked architecture; power-aware register renaming; register assignment task; register file; voltage scaling techniques; Computer architecture; Embedded computing; Embedded system; Energy consumption; Microarchitecture; Microprocessors; Pipelines; Power generation; Registers; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Innovative Architecture for Future Generation High-Performance Processors and Systems, 2004. Proceedings
Conference_Location
Maui, HI
ISSN
1537-3223
Print_ISBN
0-7695-2205-X
Type
conf
DOI
10.1109/IWIA.2004.10000
Filename
1410677
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