Title :
Power-Aware Register Renaming in High-Performance Processors Power-Aware Register Renaming in High-Performance Processors
Author :
Ayala, José L. ; López-Vallejo, Marisa ; Veidenbaum, Alexander
Author_Institution :
Dept. de Ingenieria Electron., Univ. Politecnica de Madrid
Abstract :
This work presents an efficient multi-banked architecture of the register file, and a low-power compiler support which reduces energy consumption in this device by more than a 78%. The key idea of this work is based on a quasi-deterministic interpretation of the register assignment task, and the use of the voltage scaling techniques
Keywords :
low-power electronics; parallel architectures; program compilers; high-performance processors; low-power compiler support; multibanked architecture; power-aware register renaming; register assignment task; register file; voltage scaling techniques; Computer architecture; Embedded computing; Embedded system; Energy consumption; Microarchitecture; Microprocessors; Pipelines; Power generation; Registers; Voltage;
Conference_Titel :
Innovative Architecture for Future Generation High-Performance Processors and Systems, 2004. Proceedings
Conference_Location :
Maui, HI
Print_ISBN :
0-7695-2205-X
DOI :
10.1109/IWIA.2004.10000
