DocumentCode :
2857690
Title :
Detectability analysis of small delays due to resistive opens considering process variations
Author :
García-Gervacio, José L. ; Champac, Víctor
Author_Institution :
Nat. Inst. for Astrophys., Opt. & Electron., Puebla, Mexico
fYear :
2009
fDate :
24-26 June 2009
Firstpage :
195
Lastpage :
197
Abstract :
Resistive opens in vias and interconnection lines have become an issue in modern nanometer technologies. These defects may produce small delays which are difficult to detect and may pose a reliability problem. In this paper, a statistical timing analysis framework is used to analyze the detectability of small delays due to resistive opens considering process variations. A statistical methodology to estimate the fault coverage of these defects is proposed. Using the proposed methodology, the statistical fault coverage of resistive opens producing small delays is evaluated for some ISCAS benchmark circuits.
Keywords :
circuit testing; delays; digital circuits; failure analysis; network analysis; statistical analysis; timing; ISCAS-85 benchmark digital circuits; detectability analysis; interconnection lines; process variations; reliability; resistive opens; small delays; statistical fault coverage; statistical timing analysis; vias; Astrophysics; Circuit faults; Circuit testing; Delay; Electrical fault detection; Fault detection; Integrated circuit interconnections; Probability; Semiconductor process modeling; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
On-Line Testing Symposium, 2009. IOLTS 2009. 15th IEEE International
Conference_Location :
Sesimbra, Lisbon
Print_ISBN :
978-1-4244-4596-7
Electronic_ISBN :
978-1-4244-4595-0
Type :
conf
DOI :
10.1109/IOLTS.2009.5196011
Filename :
5196011
Link To Document :
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